In the relentless pursuit of miniaturization within semiconductor technology, researchers face increasing challenges as devices approach atomic-scale thicknesses. The core dilemma arises from the physical limitations imposed on electron transport when semiconductor components become ultra-thin. A team of pioneering scientists at Pohang University of Science and Technology (POSTECH) has now unveiled a transformative approach that elegantly overcomes these obstacles. By strategically thickening only selective parts of ultra-thin tellurium transistors, their work opens a new frontier in semiconductor device engineering, promising significant advancements in performance and scalability.
As modern semiconductor devices continue to shrink, the quest for thinner channels is driven by the need to enhance transistor control and reduce leakage currents. However, thinning these channels beyond a critical dimension introduces severe drawbacks. Electrons face increased resistance at the interface between the metal electrodes and semiconductor channel, which sharply degrades the electrical performance of the device. This increased contact resistance is a major bottleneck in the design of next-generation ultra-thin transistors, especially as the semiconductor industry pushes the envelope on device speed, energy efficiency, and integration density.
Professor Byoung Hun Lee and his research team have made a breakthrough by reimagining the metal-semiconductor contact interface in tellurium-based transistors. Tellurium is an exotic but promising semiconductor material notable for its high charge carrier mobility, thermal stability at room temperature, and compatibility with low-temperature process fabrication methods. Nevertheless, its narrow band gap necessitates that the transistor channel be crafted with extreme precision, typically less than five nanometers thick, to suppress leakage current and maintain energy efficiency.
The fundamental challenge arises from the physics of the Schottky barrier—a potential energy barrier that electrons must overcome to move between the metal contact and the semiconductor. As the channel thickness decreases, this barrier widens, drastically limiting electron injection and transport. The trick of fabricating ultra-thin channels to minimize leakage inadvertently exacerbates contact resistance, thus throttling the current that flows when the device operates in its on-state. Balancing this trade-off has remained an elusive goal until now.
The innovative solution presented by the POSTECH researchers draws inspiration from established silicon semiconductor fabrication techniques, particularly the Raised Source and Drain (RSD) architecture. By deliberately increasing the semiconductor thickness only at the source and drain regions—areas directly interfacing with the metal contacts—the team succeeded in dramatically reducing electron resistance without compromising the ultra-thin channel that controls the transistor’s switching behavior. This selective thickening acts as a conduit that bypasses the detrimental effects typically seen at metal-semiconductor interfaces.
Experimentation with the RSD technique on tellurium transistors yielded impressive results. The contact resistance plummeted by a factor of 50, from an exceedingly high 97.5 kilo-ohm micrometers to an astonishingly low 1.7 kilo-ohm micrometers. Moreover, when subjected to cryogenic temperatures of minus 196 degrees Celsius, these transistors showcased a spectacular enhancement in on-state current, exhibiting more than a 17-fold increase. These dramatic improvements highlight the efficacy of localized thickness modulation in simultaneously achieving low resistance and high operational performance.
Beyond the immediate electrical advantages, this architecture’s compatibility with scalable manufacturing processes is particularly noteworthy. The team leveraged sputtering, a large-area, low-temperature deposition technique, ensuring that their approach can be integrated into standard semiconductor fabrication lines. This scalability addresses a significant hurdle in transitioning novel materials and architectures from laboratory demonstrations to industrial-scale mass production, heralding new possibilities for commercial adoption.
This advancement holds particular promise for the future of 3D integrated circuits—a technology paradigm that stacks logic and memory vertically to reduce the latency and energy overhead associated with data movement. Such structures require reliable devices that operate efficiently at temperatures below 400°C. The tellurium transistor design with localized thickness control aligns perfectly with these constraints, positioning itself as a core enabling technology for next-generation computing architectures, particularly in AI and high-performance computing applications where data throughput and power efficiency are paramount.
The concept of “localized thickness control” that underpins this innovation represents a form of band engineering that manipulates the fundamental electronic properties of semiconductor regions to optimize device function. By controlling electron energy bands through dimensional modulation, the researchers have redefined the conventional wisdom that thinner channels always equate to higher resistance. This shift in approach provides a versatile platform that can be adapted to a range of two-dimensional (2D) materials and ultra-thin semiconductors beyond tellurium, potentially catalyzing broad advancements in nanoelectronic devices.
Professor Lee emphasizes that their approach not only solves a chronic technical challenge in ultra-thin semiconductor devices but also accelerates the roadmap toward increasingly sophisticated 3D integrated circuits. These circuits are expected to revolutionize computational efficiency and integration density, enabling powerful new classes of electronic systems. The research, supported by national scientific initiatives and published in the prestigious journal ACS Nano, underscores the transformative potential of band engineering in semiconductor research.
This breakthrough illustrates a compelling example of how revisiting and adapting well-established semiconductor techniques—such as the raised source/drain structure—in conjunction with advanced materials like tellurium, can yield unforeseen leaps in performance. The successful marriage of material science innovation, precise nanofabrication, and robust device engineering showcased here highlights a roadmap for overcoming long-standing barriers in semiconductor physics and device technology.
Looking forward, the scalable and energy-efficient tellurium transistors developed by this team position themselves as crucial components in the development of future computing systems that increasingly demand miniaturization without sacrificing reliability or performance. As the demand for lower power consumption and higher processing speeds grows unabated, innovations that blend materials science ingenuity with practical device engineering such as this will be vital in shaping the semiconductor landscape of the coming decades.
Subject of Research: Ultra-thin semiconductor transistor engineering and contact resistance reduction
Article Title: Thickness-Modulated Band Engineering for Low-Resistance Contacts in Ultrathin Tellurium Transistors
News Publication Date: 27-Mar-2026
Web References: 10.1021/acsnano.5c18395
Image Credits: POSTECH
Keywords
Ultra-thin semiconductors, tellurium transistors, contact resistance, raised source/drain structure, band engineering, low-temperature fabrication, 3D integrated circuits, nanoelectronics, sputtering deposition, electron transport, Schottky barrier, high-performance computing
Tags: advanced tellurium transistor designatomic-scale semiconductor thicknessenhancing on-state current in ultra-thin transistorsimproving electron transport in semiconductorslow-resistance contacts for semiconductorsmetal-semiconductor interface optimizationnext-generation transistor scalabilityreducing contact resistance in transistorssemiconductor device performance enhancementtellurium-based transistor technologytransistor miniaturization challengesultra-thin semiconductor device engineering